1. Field of the Invention
This invention relates to circuitry used to compensate for error currents generated by common base transistors due to the Early Effect. More particularly, this invention relates to such error compensation circuitry used with folded cascode amplifiers.
2. Description of the Related Art
FIG. 1 shows circuitry for a conventional folded cascode amplifier. As shown, the folded cascode amplifier includes a differential amplifier with first and second transistors 100 and 102. The base of transistor 100 receives an inverting input (V.sub.IN-), while the base of transistor 102 receives a noninverting input (V.sub.IN+). A current source 104 connects a positive power supply rail voltage (V+) to the emitters of transistors 100 and 102. The collector of transistor 100 is connected by a resistor 110 having a value R.sub.1 to a negative power supply rail voltage (V-), while the collector of transistor 102 is connected by a resistor 112 having a value R.sub.2 to the V- power supply rail.
The current developed by the differential amplifier is "folded" back to provide a current to comply with more positive signal swings at a gain node (G) using circuitry including third and fourth transistors 120 and 122 connected in a common base configuration. The gain node G is connected to the collector of transistor 122 and to the input of a buffer 126, the output of the buffer 126 forming the output V.sub.OUT of the amplifier. Transistor 120 has an emitter connected to the collector of transistor 102 and a collector connected to the input of a current mirror 124, while transistor 122 has an emitter connected to the collector of transistor 100 and a collector connected to the output of current mirror 124. The bases of transistors 120 and 122 are connected together through a voltage bias circuit 128 to the V- power supply rail.
Under ideal conditions, resistors 110 and 112 can be replaced with electronic current sinks. With electronic current sinks, differential signal currents from the collector of transistors 100 and 102 will travel through transistors 120 and 122 largely unmodified, insensitive to differing parameters in transistors 120 and 122. However, resistors 110 and 112 are typically used instead of the current sinks because the voltage swing at the inputs V.sub.IN- and V.sub.IN+ will not be limited by a minimum operating voltage which an electronic current sink requires. When resistors 110 and 112 are utilized, the V- and V+ power supply rails may be designed to place as low as 150 mV across the resistors 110 and 112. Further, either of the inputs V.sub.IN+ or V.sub.IN- can go all the way to the V- rail voltage and the amplifier still work properly.
With resistors 110 and 112 used instead of electronic current sinks, a difference between the collector to emitter voltages (V.sub.CE S) of transistors 120 and 122 creates an offset voltage V.sub.OS across the inputs V.sub.IN+ and V.sub.IN-, requiring an unbalanced input voltage to correct. For transistor 120, almost the entire voltage potential difference between the V+ and V- rails is applied as its V.sub.CE, while only about half of the potential difference between the V+ and V- rails is applied as the V.sub.CE of transistor 122. Such a difference in V.sub.CE S occurs because the collector of transistor 122 is coupled to a the input of buffer 126 which has a nominal voltage value of 0 volts. The imbalance in the V.sub.CE voltages between common base transistors 120 and 122 causes a corresponding imbalance in the base to emitter voltage (V.sub.BE) of transistors 120 and 122 due to the Early Effect. A difference in V.sub.BE voltages in transistors 120 and 122 places unbalanced voltages across resistors 110 and 112, generating an offset voltage V.sub.OS at the inputs V.sub.IN- and V.sub.IN+. The offset V.sub.OS voltage can be represented as follows: EQU V.sub.OS =vtln((V+-V.sub.OUT)/V.sub.A)/R.sub.N g.sub.m
where vt is 26 mV at room temperature, V.sub.A is the Early Voltage of one of the respective transistors 120 or 122, g.sub.m is the transconductance of the respective transistor, and R.sub.N is the resistance of the resistor 110 or 112 connected to the respective transistor 120 or 122. The offset voltage V.sub.OS can be as much as a 10 mV.
With the offset voltage V.sub.OS as represented above, an overall gain reduction occurs for the amplifier due to the offset voltage V.sub.OS varying with the output voltage V.sub.OUT. Further, thermal noise performance is degraded, being effectively amplified and referred from the emitters of transistors 120 and 122 to the inputs of the amplifier. With V.sub.OS further varying with the supply voltage, V+, attempts to trim V.sub.OS for particular transistor parameters will be thwarted.
U.S. Pat. No. 5,168,243 entitled "Integrated High Gain Amplifier" discloses circuitry for increasing gain in a folded cascode amplifier by limiting V.sub.OS. The circuitry includes a current source driving cross coupled transistors connected to compensate for imbalance between transistors 120 and 122. The cross coupled transistors include a pair of transistors with a first transistor having a base coupled to the collector of a second transistor, and the second transistor having a base coupled to the collector of the first transistor. The current source feeds the emitters of the cross coupled transistors and is tuned to reduce any imbalance between transistors 120 and 122.